1. Field of the Invention
The present invention relates to a latch circuit having a function of monitoring process variations of semiconductor chips and to a scan chain circuit that comprises the latch circuit. Furthermore, the present invention relates to a semiconductor integrated circuit device that comprises the scan chain circuit, and a process variation judging method of the same.
2. Description of the Related Art
Recently, process variation of semiconductor chips has been increased in accordance with advanced micropattern of semiconductor integrated circuit devices. As a result, process variations tend to go out of the process control and deteriorate the yield of the products. In order to improve the yield, it is important to monitor the process variations, analyze the information, and feed it back to the manufacturing steps.
Consequently, there is a conventional technique in which an exclusive characteristic evaluation element is mounted on a semiconductor wafer, and process variation is measured with a measuring device provided outside thereof. However, as the characteristic evaluation element is formed on a scribe lane (cutting line), the process variation cannot be measured after packaging. In addition, a prober is required and a large number of measuring steps are required as well.
As a measure taken for the problems described above, conventionally, there is a first proposal for a process variation judging circuit that is capable of judging process variations automatically at a high speed, as disclosed in Japanese Published Patent Literature (Unexamined Patent Publication H11-145237). In this proposal, the process variation judging circuit is mounted within a semiconductor chip, and the process variation of the chip can be measured by outputting information of the process variation of each semiconductor chip through being converted to binary signals.
Further, conventionally, there is a second proposal for a substrate bias control circuit that reduces the process variations. In the second proposal, a device for monitoring the process variation is formed within a semiconductor chip, and a substrate bias is applied to a substrate terminal of a MOS transistor of the semiconductor chip to improve the characteristic of the device. Herewith, the process variation of the MOS transistor can be reduced.
However, it becomes a factor for increasing the size (area) of the semiconductor chip to mount the process variation judging circuit to each semiconductor chip as in the first proposal. Furthermore, the second proposal cannot deal with such a fault that it does not work at a desired operating frequency due to the process variation within the chip, since it has no device improving unit such as a substrate bias control circuit. However, it is more difficult to mount a plurality of process variation judging circuits within a semiconductor chip in terms of the area as described above. Therefore, it is not possible in the first proposal to deal with a plurality of process variations.
In the structure of the second proposal, the monitor circuit monitors the process characteristic only at a certain point within the chip. Therefore, when that certain point does not reflect the process characteristic within the chip, the effect of correcting the variation is diminished.